1. Field of the Invention
The present invention relates generally to voltage generating devices and operating methods thereof and, more particularly, to a voltage generating device capable of generating a voltage at an arbitrary level with small power consumption and an operating method thereof.
2. Description of the Background Art
At present a semiconductor integrated circuit device such as a semiconductor memory device or the like is provided with a circuit which supplies a predetermined constant voltage to a predetermined part of the semiconductor integrated circuit device at least in a period in which an internal circuit of the semiconductor integrated circuit operates.
FIG. 7 is a schematic diagram illustrating a structure of a half Vcc generating circuit, which is an example of such a circuit.
A half Vcc generating circuit is generally used in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) or the like for precharging a bit line or an I/O line to a potential which is half a supply potential Vcc (normally 5 V), for fixing one electrode of a capacitor constituting a memory cell to a potential which is half the supply potential Vcc, in a period in which reading and writing of data are not performed, and so forth.
FIG. 8 is an equivalent circuit diagram illustrating a structure of a memory cell of a DRAM. Referring to FIG. 8, each memory cell of a DRAM includes a MOS transistor Tr, which has a gate connected to a word line WL, a drain connected to a bit line BL, and a source, and a capacitor C. One electrode of the capacitor C is connected to the source of the transistor Tr, and another electrode is connected to a so-called cell plate, a substrate portion in which a memory cell array is formed, in common with electrodes of capacitors C of all other memory cells (not shown). The cell plate is fixed to a potential which is half a supply potential Vcc to fix the potential of one electrode of the capacitor of each memory cell.
A bit line and an I/O line transmit data of logical values "1" and "0" as rise of potential (or fall of potential) and fall of potential (or rise of potential), respectively, to a circuit or signal line in the next stage. Therefore, if the bit line and I/O line are precharged to Vcc/2, which is a potential intermediate between the supply potential Vcc and a ground potential 0 V, in reading of data, it becomes easy for the potentials of the bit line and the I/O line to change according to whether read data is of the logical value "0" or of the logical value "1".
Next, the structure and operation of a conventional half Vcc generating circuit will be described with reference to FIG. 7.
A conventional half Vcc generating circuit includes resistors 1-3, which are connected in series with each other between a supply terminal Tcc to be supplied with a supply potential Vcc and ground GND, and an N-channel MOS transistor 4 and a P-channel MOS transistor 5, which are connected in series with each other between the supply terminal Tcc and the ground GND. The gates of transistors 4 and 5 are connected to the connection point between registers 1 and 2 and the connection point between registers 2 and 3, respectively. The potential of the connection point (a node N3) between transistors 4 and 5 is used as an output voltage Vout of the half Vcc generating circuit.
Current flows from the supply terminal Tcc through resistors 1-3 to the ground GND in a period in which the supply potential Vcc is supplied to supply terminal Tcc, so that the potential of the connection point between resistors 1 and 2 is a potential lower than the supply potential Vcc by a voltage drop caused by resistor 1, and the potential of the connection point between resistors 2 and 3 is a potential lower than the potential of the connection point between resistors 1 and 2 by a voltage drop caused by resistor 2. The values of resistance of respective resistors 1-3 are set so that the potential of the connection point (a node N1) between resistors 1 and 2 is a potential (Vcc/2+Vthn) which is higher than a potential Vcc/2, which is half the supply potential Vcc, by the threshold voltage Vthn of transistor 4 and so that the potential of the connection point (a node N2) of registers 2 and 3 is a potential (Vcc/2-Vthp) which is lower than the potential Vcc/2, which is half the supply potential Vcc, by the threshold voltage Vthp of transistor 5.
Transistor 4 is brought to ON state and supplies positive charge from the supply terminal Tcc to node N3 in a case where its gate potential Vgn is higher than a potential (Vout+Vthn) which is higher than the potential Vout of node N3 by its threshold voltage Vthn, i.e. in a case where the following expression is realized. EQU Vout&lt;Vgn-Vthn
Transistor 5 is brought to ON state and supplies negative charge from the ground GND to node N3 in a case where its gate potential Vgp is lower than a potential (Vout-Vthp) which is lower than the potential Vout of node N3 by its threshold voltage Vthp, i.e. in a case where the following expression is realized. EQU Vout&gt;Vgp+Vthp
Therefore, in a case where the potentials of node N1 and N2 are (Vcc/2+Vthn) and (Vcc/2-Vthp), respectively, if the potential Vout of node N3 becomes higher than Vcc/2, transistor 4 is brought to OFF state while transistor 5 is brought to ON state, so that the potential Vout of node N3 is lowered. However, if the potential Vout of node N3 becomes lower than Vcc/2, transistor 5 is brought to OFF state while transistor 4 is brought to ON state, so that the potential of node N3 rises. Accordingly, the potential Vout of node N3 is controlled to be always approximately Vcc/2 by setting the gate potentials Vgn and Vgp of transistors 4 and 5 to such potentials. In a state wherein the potential Vout of node N3 is stable at Vcc/2, transistors 4 and 5 are both in OFF state, so that no current flows from the supply terminal Tcc through transistors 4 and 5 to the ground GND.
FIG. 11 is a schematic diagram illustrating a structure of a substrate bias circuit, which is another example of a circuit which generates a voltage at a predetermined level in a semiconductor integrated circuit device.
A substrate bias circuit is provided in a semiconductor integrated circuit device for preventing malfunction of a circuit and degradation of electric characteristics of a circuit due to fluctuation in the potential of a semiconductor substrate.
FIG. 13 is a schematic diagram illustrating an example of a general structure of a data providing circuit in a semiconductor integrated circuit device. Referring to FIG. 13, the providing circuit generally includes two N- channel MOS transistors 12, 13 connected in series with each other between a supply potential T.sub.DD, which is to be supplied with a supply potential V.sub.DD predetermined according to the potential level of an input/output signal, and ground GND. Potentials V1, V2 at levels complementary to each other and corresponding to data to be provided are applied from a circuit (not shown) in the preceding stage to the gates of transistors 12 and 13, respectively. The connection point between transistors 12 and 13 is connected, as an output terminal of the providing circuit, to an I/O pin (not shown).
Accordingly, in a period in which transistor 12 is in ON state, transistor 13 is in OFF state, and, conversely, in a period in which transistor 13 is in ON state, transistor 12 is in OFF state. Therefore, a high potential V.sub.DD of the supply terminal T.sub.DD or a low potential Vss of the ground GND appears onto the connection point between transistors 12 and 13 according to the output potentials v1, v2 of a circuit in the preceding stage.
If the potential of a semiconductor substrate becomes higher than the potential of the I/O pin, charge flows from an N.sup.+ region to a P well region in such a providing circuit. FIG. 14 is a diagram for explaining such a phenomenon. FIG. 14 shows a cross sectional view of the structure of transistor 12 (or 13) in FIG. 13.
Referring to FIG. 14, transistor 12 (or 13) includes N.sup.+ regions 200 and 300 formed as a drain and a source, respectively, on a P well 100 formed in a semiconductor substrate 1000 and a gate electrode 400 formed across the portion between N.sup.+ regions 200 and 300 on P well 100 with an insulating film (not shown) interposed therebetween. One N.sup.+ region 200 is connected to a supply terminal T.sub.DD (or ground GND) to receive a high potential T.sub.DD (or a low potential Vss), and the other N.sup.+ region 300 is connected to an I/O pin. Gate electrode 400 receives a signal v1 (or v2) from a circuit in the preceding stage of the providing circuit.
In a case where the potential of P well 100 is 0 V or more, if a negative potential is externally supplied to the I/O pin, for example, the PN junction formed by N.sup.+ region 300 and P well 100 is brought into a forward bias state, so that electrons e.sup.- are supplied from N.sup.+ region 300 to P well 100. If this providing circuit is used in a DRAM, for example, the electrons e.sup.- thus flowing into P well 100 cancel positive charge accumulated in a capacitor C (see FIG. 8.) in a memory cell, so that it happens that storage data in the memory cell is destructed.
In order to avoid such a phenomenon, the potential of semiconductor substrate 100, i.e. the potential of P well 100, may be held at a predetermined negative potential so that the PN junction formed by N.sup.+ region 300 and P well region 100 is not brought to the forward bias state.
FIG. 15 is a schematic diagram illustrating a structure of arbitrary one memory cell in a DRAM.
Referring to FIG. 15, when data is written, the potential of a word line WL is brought to a potential (normally a supply potential) of a high level which is considerably higher than the threshold voltage of a transistor Tr for a constant period, while the potential of a bit line BL is brought to the high level (in a case where data to be stored in a memory cell MC is "1") or a low level (in a case where the data to be stored in the memory cell MC is "0") according to the data to be stored in the memory cell MC. This causes a capacitor C to be charged or discharged. After a lapse of the constant period, the potential of the word line WL is brought to a potential (normally a ground potential) at the low level, which is sufficiently lower than the threshold voltage of the transistor Tr, so that in a case where the capacitor C is charged, charge accumulated in the capacitor C does not flow through the transistor Tr to the bit line BL.
When data is read, the potential of the word line WL is fixed at the high level for a constant period, while change in the potential of the bit line BL is detected. If charge is accumulated in the capacitor C, positive charge is supplied from the capacitor C through the transistor Tr to the bit line BL in the constant period, so that the potential of the bit line BL rises. If charge is not accumulated in capacitor C, positive charge is supplied from the bit line BL through the transistor Tr to the capacitor C in the constant period, so that the potential of the bit line BL lowers. Thus, rise of potential is caused in the bit line BL in a case where data "1" is stored in the memory cell MC, while fall of potential is caused in the bit line BL in a case where data "0" is stored in the memory cell MC, so that it is possible to discriminate data stored in the memory cell MC by detecting change in the potential of the bit line BL.
Now, in a period in which neither writing of data nor reading of data is performed, the potential of the word line WL is brought to the low level, so that the transistor Tr is brought to OFF state and cuts off the current flowing between the bit line BL and the capacitor C. However, in a case where the threshold voltage of the transistor Tr is too low, the transistor Tr is brought to ON state by only a little rise of potential in the word line WL due to some cause in a period in which neither of writing of data nor reading of data is performed, so that charge accumulated in the capacitor C leaks through the transistor Tr to the bit line BL. As a result, storage data of the memory cell MC is destructed. In order to avoid such a phenomenon, it is necessary that the threshold voltage of the transistor Tr is set high.
Now, the relation between the threshold voltage V.sub.th of an N-channel MOS transistor (See FIG. 14.) and the square root of the absolute value .vertline.V.sub.SB .vertline. of the potential V.sub.SB of a P well 100 in which the N-channel MOS transistor is represented as V.sub.th =V.sub.tho +.alpha. (.vertline.V.sub.SB .vertline.).sup.1/2. V.sub.th expresses the threshold voltage of the N-channel MOS transistor in a case where V.sub.SB =0 V, and .alpha. is a constant. Specifically, the threshold voltage of the N-channel MOS transistor is larger as the potential of the substrate in which the N-channel MOS transistor is formed is a negative potential with a larger absolute value. Accordingly, in order to suppress generation of leakage of charge from the capacitor C to the bit line BL due to fluctuate in the potential of the word line WL, a semiconductor substrate in which a memory cell MC is formed may be held at an appropriate negative potential. As described above with reference to FIGS. 13 to 15, it is necessary to bias a semiconductor substrate to a certain constant negative potential V.sub.BB in order to solve various disadvantages. A substrate bias circuit is a circuit provided for that purpose.
Next, referring to FIGS. 11 and 12, the structure and operation of a conventional substrate bias circuit will be described.
FIG. 12 is a timing chart showing potential waveforms of control signals .PHI.1, .PHI.2 supplied to the substrate bias circuit in FIG. 11.
The substrate bias circuit includes inverters 5 and 9 receiving driving signals .PHI.1 and .PHI.2 of phases opposite to each other as shown in FIG. 12 (a) and (b), respectively, a capacitor 6 and a P-channel MOS transistor 8 which are connected in series with each other between an output terminal of inverter 5 and ground GND, and a capacitor 10 and a P-channel MOS transistor 11 which are connected in series with each other between an output terminal of inverter 9 and the ground GND. The potential of the connection point (a node N5) between capacitor 10 and transistor 11 is applied to the gate of transistor 8, and the ground potential is applied to the gate of transistor 11.
The substrate bias circuit further includes a P-channel MOS transistor 7 which is diode-connected. The gate of transistor 7 is connected to the connection point (a node N4) between capacitor 6 and transistor 8. The output voltage of inverter 5 is used as back gate voltages of transistors 7 and 8. The output voltage of inverter 9 is used as a back gate voltage of transistor 11.
The output potential of transistor 7 is applied as the output potential V.sub.BB of the substrate bias circuit to a semiconductor substrate (not shown).
If the potential of the driving signal .PHI.2 is switched from a high level to a low level (a time t1 in FIG. 12 (b)) in a period in which the potential of the driving signal .PHI.1 is at the low level, the potential of node N5 is raised by coupling of capacitor 10. The back gate voltage of transistor 11 is brought to the high level to cause transistor 11 to be brought to ON state, so that node N5 is electrically connected to the ground GND. As a result, the potential of node N5 is lowered. Such fall in the potential of node N5 causes transistor 8 to be brought to ON state, so that positive charge is pulled out of node N4 through transistor 8 to the ground GND.
Next, if the potential of the driving signal .PHI.1 is switched from the low level to the high level (a time t2 in FIG. 12), the output potential of inverter 5 is brought to the low level, so that charges are discharged from capacitor 6. This causes negative charge to be supplied from capacitor 6 to node N4, so that the potential of node N4 starts to fall to be negative.
The potential of node N5 is the ground potential 0 V, so that if the potential of node N4 becomes a negative potential, transistor 8 is brought to OFF state so that node N4 is electrically separated from the ground GND. If the potential of node N4 becomes such a negative potential, transistor 7 is brought to ON state. Accordingly, negative charges are discharged from the capacitor 6 through node N4 and transistor 7 in response to switching of the driving signal .PHI.1 from the low level to the high level.
The supply of the negative charge from capacitor 6 to node N4 causes the potential of node N4 to be finally a negative potential (-Vcc) having the same absolute value as that of the supply potential Vcc. Accordingly, with such discharge of negative charges, the output potential V.sub.BB of transistor 7 becomes a potential (-Vcc+Vthp) which is higher than the negative potential (-Vcc) having the same absolute value as that of the supply potential by the threshold voltage Vthp of transistor 7.
Next, if the driving signal .PHI.1 is switched from the high level to the low level in a period in which the potential of the driving signal .PHI.2 is at the low level (a time t3 in FIG. 12), the potential of node N4 rises, so that transistor 7 is brought to OFF state. This causes node N4 to be electrically separated from the semiconductor substrate.
Next, if the driving signal .PHI.2 is switched from the low level to the high level (a time t4 in FIG. 12), the output potential of inverter 9 is brought to the low level, so that negative charge is supplied from capacitor 10 to node N5, and thus the potential of node N5 becomes a negative potential. The back gate voltage of transistor 11 is brought to the low level to cause transistor 11 to be brought to OFF state, so that all the negative charge discharged from capacitor 10 is supplied to the gate of transistor 8. The potential of node N4 is the ground potential 0 V, so that transistor 8 is brought to ON state in response to the supply of the negative charge to the gate. This causes the potential of node N4 to return to the ground potential 0 V.
By repeating the circuit operation as described above, an approximately constant negative potential (-Vcc+Vthp) is provided from transistor 7 to bias the semiconductor substrate.
As described above, a voltage generating circuit which generates a voltage at a predetermined level in a semiconductor integrated circuit device is generally a circuit such as a half Vcc generating circuit (FIG. 7) in which the gate potentials of a plurality of MOS transistors connected in series with each other are set to an appropriate potential obtained by division of resistance so as to fix the connection points between those MOS transistors to a desired potential or a circuit of a so-called charge pumping type such as a substrate bias circuit (FIG. 11) in which charging and discharging of a capacitor are performed alternately to release a constant amount of charge in constant timing so as to generate a desired voltage. However, the circuits of such structures have problems as will be described in the following.
First, problems of a circuit of the former structure will be described with reference to FIGS. 7, 9 and 10.
FIG. 9 is a cross sectional view illustrating a structure of transistor 4 in FIG. 7. FIG. 10 is a cross sectional view illustrating a structure of transistor 5 in FIG. 7.
Referring to FIG. 7, a through current flows constantly from the supply terminal Tcc through resistors 1-3 to the ground GND in a period in which the supply potential Vcc is supplied to the supply terminal Tcc, i.e. in a period in which the half Vcc generating circuit operates. Accordingly, the power consumption of the conventional half Vcc generating circuit is large, and there is a problem that inhibits the approach to low power consumption, which is been requiring in many fields including the field of semiconductor integrated circuit devices at the present time.
Although the threshold voltage Vthn of transistor 4 and the threshold voltage Vthp of transistor 5 are set so that both of transistors 4 and 5 are not brought to ON state at the same time, if the threshold voltage of transistor 4 is different from the set value Vthn, or the threshold voltage of transistor 5 is different from the set value Vthp, there is a period in which both of transistors 4 and 5 are in ON state, so that a through current flows from the supply terminal Tcc through transistors 4 and 5 to the ground GND.
For example, if the threshold voltage of transistor 4 is lower than the set value Vthn, transistor 4 is in ON state even if the potential Vout of node N3 is higher than Vcc/2. On the other hand, if the potential Vout of node N3 is higher than Vcc/2, transistor 5 is in ON state. Accordingly, both of transistors 4 and 5 are in ON state, and a through current flows between the supply terminal Tcc and the ground GND.
As described above, the conventional half Vcc generating circuit also has a problem that a through current is increased due to irregularity in the threshold voltage of a MOS transistor in manufacture, i.e. the power consumption tends to be increased.
In order to reduce the current flowing between resistors 1 to 3, the values of resistance of resistors 1 to 3 may be increased. A resistive element is provided as a so-called diffusion resistor formed by diffusing impurities of an N type or a P type on a semiconductor substrate. The value of resistance of a diffusion resistor is determined by the ratio between the lengths of two sides of a region (normally rectangular) in which impurities are diffused. The value of resistance of a resistor element is larger as the ratio of the length of the side parallel to the direction of the flow of current to the length of another side vertical to the direction of the flow of the current is larger. Therefore, in order to increase the values of resistance of resistors 1 to 3 in FIG. 7, the layout areas of these respective resistors 1-3 on the semiconductor substrate are increased. Such increase in the layout areas of the components is unfavorable because it inhibits large scale integration of a semiconductor integrated circuit device.
Furthermore, also in the view of a circuit operation of the conventional half Vcc generating circuit as will be described in the following, it difficult to reduce the current flowing between resistors 1 to 3.
It is assumed that the potential Vout of node N3 becomes a potential (Vcc/2-.alpha.) which is lower than a potential (Vcc/2) to be originally taken because of influence of the capacitance of a load to which the potential Vout is to be applied or the like. In such a case, transistor 4 is brought to ON state, so that in FIG. 9, a channel is formed between one N.sup.+ region 200 and the other N.sup.+ region 300. This causes an insulating film (not shown) under gate electrode 400 to function as a capacitor which receives the potential of node N1 at one electrode and receives the potential of the channel at another electrode. The potential of the channel is between the potential of N.sup.+ region 200, i.e. the potential Vout (Vcc/2-.alpha.) of node N3, and the potential of N.sup.+ region 300, i.e., the supply potential Vcc.
On the other hand, if the potential Vout of node N3 becomes a potential (Vcc/2+.alpha.) which is higher than the potential (Vcc/2) to be originally taken, transistor 4 is brought to OFF state, so that in FIG. 9, no channel is formed between N.sup.+ regions 200 and 300. Accordingly, in such a case, the insulating film under the gate electrode 400 operates as a capacitor which receives the potential of node N1 at one electrode and receives the potential of P well 100 at another electrode. P well 100 is biased to approximately -3 V by a substrate bias circuit or the like, for example, (in a case where the supply potential Vcc is 5 V).
Accordingly, the capacitance between the gate of transistor 4 and the drain of transistor 4 is changed by the switching operation of transistor 4 due to fluctuations in the potential Vout of node N3, so that a charge and discharge current for the capacitance between the gate and drain flows between node N1 and the gate of transistor 4. As a result, the potential of transistor 4 fluctuates from the potential (Vcc/2+Vthn) to be originally taken. Such a phenomenon occurs in transistor 5 as well.
Specifically, if the potential Vout of node N3 is higher than the potential (Vcc/2) to be originally taken, transistor 5 is brought to ON state, so that in FIG. 10, a channel is formed between P.sup.+ regions 600 and 700. Therefore, an insulating film (not shown) under gate electrode 800 operates as a capacitor which receives the potential of node N1 at one electrode and receives the potential of the channel at another electrode. In such a case, the potential of the channel is between the potential of P.sup.+ region 600, i.e. the ground potential 0 V, and the potential of P.sup.+ region 700, i.e. the potential Vout Vcc/2+.alpha.) of node N3.
On the other hand, if the potential Vout of node N3 is lower than the potential (Vcc/2) to be originally taken, transistor 5 is in OFF state, so that no channel is formed between P.sup.+ regions 600 and 700. Therefore, the insulating film under gate electrode 800 operates as a capacitor which receives the potential of node N1 at one electrode and receives the potential of N well 500 at another electrode. N well 500 is normally biased to approximately 5 V (in a case where the supply potential Vcc is 5 V).
Accordingly, the switching operation of transistor 5 due to the fluctuations in the potential Vout of node N3 changes the capacitance between the gate and drain of transistor 5. Therefore, a charge and discharge current for the capacitance between the gate and the drain flows between node N2 and the gate of transistor 5, so that the gate potential of transistor 5 fluctuates from the potential (VCc/2-Vthp) to be originally taken.
As described above, if the gate potentials of transistors 4 and 5 fluctuate, the potential of node N3 also fluctuates, so that a correct potential (Vcc/2) is not provided from the half Vcc generating circuit. In order to avoid such a problem, it is necessary to increase the current flowing from the supply terminal Tcc through resistors 1-3 to the ground GND so that the current flowing between node N1 and the gate of transistor 4 for charging and discharging of the capacitance between the gate and drain of transistor 4 and the current flowing between node N2 and the gate of transistor 5 for charging and discharging of the capacitance between the gate and drain of transistor 5 are sufficiently smaller as compared with the current flowing from the supply terminal Tcc through resistors 1-3 to the ground GND.
If the current flowing from the supply terminal Tcc through resistors 1-3 to the ground GND is sufficiently larger than such a charge and discharge current, the potential of node N1 is not fluctuated so largely by the current flowing from node N1 to the gate of transistor 4 and the current flowing from the gate of transistor 4 to node N1, and, similarly, the potential of node N2 is not fluctuated so largely by the current flowing from node N2 to the gate of transistor 5 and the current flowing from the gate of transistor 5 to node N2.
However, increase in the current flowing from the supply terminal Tcc to the ground GND, i.e. the through current, leads to further increase in the power consumption.
As described above, a voltage generating circuit of such a structure as representated by the conventional half Vcc generating circuit has a problem that it is disadvantageous to the realization of low power consumption and large scale integration.
Now, problems of the latter voltage generating circuit will be described with reference to the substrate bias circuit in FIG. 11.
The latter voltage generating circuit is constructed so that negative charge is discharged from capacitor 6 in a constant cycle to turn on diode-connected MOS transistor 7 provided for supplying the discharged negative charge to a semiconductor substrate. Therefore, the output voltage V.sub.BB of a substrate bias circuit is limited to a voltage (-Vcc+Vthp) which is higher than a negative voltage having the same absolute value of that of a signal for charging capacitor 6, i.e. the maximal voltage level Vcc of an output signal of inverter 5, by the threshold voltage Vthp of MOS transistor 7. Therefore, according to the conventional substrate bias circuit, it is impossible to bias the semiconductor substrate to an arbitrary potential.
Specifically, it is only possible to adjust the substrate bias voltage only by adjusting the threshold voltage Vthp of the MOS transistor. The threshold voltage Vthp of the MOS transistor is nearly 0.8 V, and it cannot be changed so largely even by adjusting conditions of manufacture of the MOS transistor or the like. Therefore, in a semiconductor integrated circuit device in which the supply potential Vcc is 5 V, for example, the substrate bias voltage V.sub.BB is specified to be nearly -4.2 V.
However, recently, it is proposed to use a supply potential Vcc of approximately 3 V, which is lower than 5 V, and to bias the semiconductor substrate to a negative potential higher than in the case of conventional devices in order to further enhance the operating speed of the semiconductor integrated circuit device. The operating speed of the semiconductor integrated circuit device is known to become slower as the semiconductor substrate is biased to a lower negative potential. However, it is impossible to avoid such problems as described above unless the semiconductor substrate is biased to a potential which is low to a certain extent.
For example, in a semiconductor integrated circuit device in which the supply voltage is 5 V, if the substrate bias voltage V.sub.BB is lowered to nearly -4.2 V, it is difficult to further enhance the operating speed of the device.
Accordingly, in order to avoid such problems and further enhance the operating speed of the device as well, it is currently proposed to set the supply voltage Vcc to about 3 V and set the substrate bias voltage V.sub.BB to about -1.5 V, for example.
However, according to the conventional substrate bias generating circuit, the substrate bias voltage V.sub.BB is limited to -3 V+0.8 V, i.e. about -2.5 V.
As described above, according to the latter voltage generating circuit, its output voltage is determined almost uniquely by the supply voltage Vcc, so that it is difficult to further enhance the operating speed of a semiconductor integrated circuit device.